Inverter having forced turn-off

ABSTRACT

An electrical inverter circuit for converting d.c. electrical input into an a.c. electrical output involving the control of active switch elements in the primary of an output transformer circuit by, in part, providing a further controllable active element in circuit with the active element switches such that the primary winding current also flows therethrough. Synchronous control means are provided for synchronously controlling this further active element so as to increase its electrical impedance during at least a portion of each switching transition of the active element switch means so as to further aid and promote the rapid and efficient transitioning of the active element switches. Various alternative circuits are shown for this and for detecting the switch point as a function of primary transformer winding current and for further controlling the transition of the active switches in combination with the increased electrical impedance of the further controllable active element in circuit therewith.

INVERTER HAVING FORCED TURN-OFF

This invention generally relates to an electrical inverter circuit forconverting a d.c. electrical input into an a.c. electrical output. Inparticular, this invention relates to an improved control for activeelement switches utilized to alternately switch the d.c. electricalinput through the primary winding of a transformer thus giving rise toan a.c. output in a secondary winding thereof.

Switching mode power supplies of this general type are becomingincreasingly popular for a variety of applications as evidenced by suchrecent publications as various articles in the Monday, Sept. 23, 1974issue of Electronic Engineering Times and the July 1974 issue of MullardTechnical Communications No. 123. Switching mode power suppliesconforming to this general classification are also found in issued U.S.Pat. such as, for instance, Nos. 3,161,834; 3,136,958; 3,546,626; and3,758,841.

Our own earlier U.S. Pat. No. 3,781,638 issued Dec. 25, 1973 describes aswitching mode power supply utilizing active element switches (e.g.,transistor devices) for alternately switching a d.c. supply currentthrough the primary windings of a transformer thus giving rise to ana.c. output in a secondary winding. The correct phase and magnitude ofcontrol power for maintaining sustained repetitive switching operationof the switching transistors is obtained in this earlier circuit from atertiary low voltage winding on the output transformer. In addition, ourearlier issued and above referenced patent (which earlier patent iscommonly assigned with the instant application) also utilizes a controltransistor which helps to positively turn the switching transistors"off" at the end of each half-cycle of inverter operation as determinedby detecting the predetermined level of primary winding current.

The instant invention relates to further improvements in the controlcircuitry for controlling the switching transistors in a switching modeinverter and, in the preferred exemplary embodiment, to an improvedswitching control for the particular type of switching mode inverterdescribed in our earlier issued and above referenced U.S. Pat. No.3,781,638.

Some of the features of this invention are also disclosed in conjunctionwith another invention of John P. Walden in a commonly assignedcopending United States Patent Application filed concurrently herewithand entitled DC TO AC INVERTER HAVING IMPROVED SWITCHING EFFICIENCY,OVERLOAD AND THERMAL PROTECTION FEATURES.

In the past, switching control over the switching transistors has beeneffected primarily by influencing the bias current available at thecontrol leads of such active element switches. For instance, in ourabove referenced patent, a switching control transistor detects a switchpoint at a predetermined level of primary winding current and, inresponse thereto, substantially shunts the base elements of theswitching transistors to ground potential thus dissipating any forwardbias currents and thereby turning these switching transistors off.

It has now been discovered that the switching operation can be enhancedand its efficiency can be improved by incorporating still furtherswitching control features. For example, the instant invention includesthe provision of a further controllable active element means in circuitwith the active element switches such that the primary winding currentalso flows through this further controllable element. Synchronouscontrol means are also provided for synchronously controlling thefurther active element so as to increase its electrical impedance duringat least a portion of each switching transition for the active elementswitches. This action, in the preferred exemplary embodiments, causes asimultaneous and synchronous rise in emitter voltage for the switchingtransistors at the same time that the base voltage is drasticallylowered. Since, in the exemplary embodiments, NPN switching transistorsare utilized, this combined and synchronous switching control much morequickly and efficiently reverse biases the base-emitter junction of theswitching transistors and effects the desired switching transition.

It has also been discovered that the increased voltage across thisfurther controllable active element (due to its increased electricalimpedance) may be utilized to further control the dissipation of anyforward biasing currents at the control or base electrode of theswitching transistors. This detected increase in voltage is alsoutilized in some embodiments of the invention as a feedback controlsignal for insuring that the further controllable active element ismaintained in its high impedance state throughout the switchingtransition period.

The preferred current apparatus of this invention involves a currentmeasuring element (e.g., a known electrical impedance, etc.) connectedserially in a common collector-emitter switching transistor circuittogether with a further controllable active element such that theprimary winding current flowing to either of the switching transistorsalso flows through the current measuring element. Current leveldetection means (e.g., a transistor device with its control elementconnected thereto) is controlled by the current measuring element to, inturn, control the electrical impedance of the further controllableactive element (e.g., a transistor device). However, other alternativesof current detection means have also been discovered to have potentialadvantages. Accordingly, such alternate means also form a part of thisinvention.

One such alternate current detection means involves a voltage dividerconnected across the current measuring means and a further controllableactive element in conjunction with a voltage level detection means.Another current detection means comprises a current monitor such as aninverting current source connected only to the control element of thefurther controllable active element means thus eliminating the need forany extra impedance means in the primary winding current path.

Another alternate embodiment of this invention provides independent baseand emitter controls for the two switching transistors and a common peakcurrent detector for controlling the independent base and emittercontrol circuits.

Further alternative embodiments of this invention utilize a currentsensitive latch means (e.g., an SCR like arrangement of NPN and PNPtransistor devices) to provide a switching control hysteresis effect forinsuring that positive switching control is maintained during theswitching transition period until conditions are insured to be properfor completing the transition cycle.

These and other objects and advantages of the invention will be moreclearly apparent upon reading the following detailed description of theinvention taken in conjunction with the accompanying drawings of which:

FIG. 1 is a detailed schematic diagram of a presently preferredembodiment of the invention;

FIG. 2 is a detailed schematic diagram of an alternate embodiment ofthis invention;

FIG. 3 is a detailed schematic diagram of still another alternateembodiment of this invention;

FIG. 4 is a detailed schematic diagram of yet another alternateembodiment of this invention;

FIG. 5 is a schematic diagram of a portion of still another alternateembodiment of this invention; and

FIG. 6 is a detailed schematic diagram of a still further alternateembodiment of this invention.

Although the inverter of this invention will have many possibleapplications, one of the presently anticipated applications for thisinvention is its use in a line cord power supply unit. Such units arepresently contemplated as very small volume and lightweight devices forplugging directly into a conventional 110-120 volt household a.c.receptacle. The output of such an unit is presently contemplated as alow voltage d.c. output for powering common household appliances withinthe power rating of the unit.

In such applications, it is necessarily to make the maximum usage of thelimited available volume and weight. Accordingly, it is presentlycontemplated that the a.c. input would be directly converted to d.c. forpowering a d.c./a.c. inverter (such as that described herein) operatingat a relative high frequency) (e.g. 25 kHz). This high frequency a.c.output from the inverter would then be rectified and delivered as thefinal low voltage d.c. output from the line cord power supply unit.

As should be appreciated, operation of the inverter at such a highfrequency permits transformer isolation and voltage conversion of fairlysignificant power levels without necessitating bulky and weightytransformer core materials. It is also contemplated that much of theelectronic circuitry involved in elements such as the inverter wouldhave to be constructed in a monolithic integrated form to meet thedesign restraints in such a power supply application. This invention isespecially adapted to such an application since the circuitry involvedherein is especially adapted for monolithic integrated circuitconstruction techniques.

To obtain high efficiency in such a switched mode power supply, it hasbeen discovered that the switching losses in the switching transistorsmust be drastically reduced by properly biasing the transistor duringturn off (e.g., during switching transition periods). Furthermore, thiscontrolled switching bias must be obtained without the use of capacitorsor auxiliary power supplies to enhance the adaptability of suchinverters for applications such as the line cord power supply mentionedabove.

Referring to FIG. 1, the starting circuit comprising Q6, D10, R8, R9,R10 and C2 will first be described. Initially, capacitor C2 isdischarged. When a d.c. input is first applied to the inverter of FIG.1, capacitor C2 begins to charge through resistor R10 with anappropriately preselected time constant. When the trigger voltage of Q6is reached, Q6 breaks down and supplies a starting pulse of current tothe base of Q1 through R9 and D10 and to the base of Q3 through R8.Thus, Q3 is forward biased to its "on" condition to complete the commonemitter circuit for switching transistors Q1 and Q2. At the same time,Q1 is forward biased so as to turn Q1 to its on state thus permittingcurrent to flow from the d.c. source through the center tap connectionof the primary windings, through Q1, Q3 and Z1.

As will be explained in more detail below, transistor Q4, during normalinverter operation, is turned to its on state each half-cycle ofinverter operation. At these times, the accomulated charge on C2 isdischarged through R11 and D11 thus insuring that C2 never again reachesthe trigger level of Q6 during normal inverter operation. Of course,should normal inverter operation be interrupted for some reason, then C2would again be permitted to charge to the trigger level of Q6.

As the current builds up in the primary winding W2, voltages are inducedin the secondary output winding W4 and in a low voltage tertiary windingW3. As can be seen from the dot convention shown in FIG. 1, the currentflow generated in tertiary winding W3 by current flow through W2 and Q1,etc., is in the proper direction to supply base current to Q1 throughR2, Q1, Q3, Z1 and D1. At the same time, base current is provided to Q3via D4, R3, Q3, Z1 and D1. Accordingly, once inverter operation isinitiated by a starting pulse from Q6, the switching transistor Q1 andcontrol transistor Q3 are maintained in their on conditions byself-induced currents in tertiary winding W3.

The primary winding current passing through W2, Q1, Q3 and Z1 is afunction of both the load and transformer core characteristics. As timeprogresses, the primary winding current increases due to magnetizingcurrent and, ultimately, it increases quite rapidly as the magneticcircuit of the transformer approaches saturation. By properly selectingZ1, the transistor Q5 will be caused to turn on due to the voltage dropacross Z1 just at the onset of magnetic core saturation and/or duringoverload conditions which would cause excessive current through Z1. Thefunction then of Z1 in the exemplary embodiment of FIG. 1 is to maintainthe base-emitter voltage of Q5 below is intrinsic turn on voltage leveluntil the primary winding current flowing therethrough reaches apredetermined level. In effect then, Z1 in combination with Q5 acts as acurrent detector with Z1 being a current measurement means and Q5 beinga current level detector. Ideally, a constant current sink would beutilized for Z1 but Z1 can also be successfully approximated by aresistor, diode, transistor or combinations thereof in a monolithicintegrated circuit construction as will be apparent.

As shown in FIG. 1, the current detection circuit is common to both themain power transistors Q1 and Q2. It is also possible to utilizeindividual current detection circuits for each switching transistor;however, the use of a single current detector as in FIG. 1 is preferredsince it reduces the number of components which must be included in theintegrated circuit construction and provides for a more symmetricaloperation of the inverter.

When the predetermined level of primary winding current is detected byZ1 and Q5, Q5 turns on as noted above thus diverting base current fromQ3 and thus permitting Q3 to come out of saturation thereby increasingthe electrical impedance in the collector-emitter circuit of Q3. SinceQ3 is no longer saturated, its collector voltage is now permitted torise bringing with it the emitter voltages of switching transistors Q1and Q2 to which it is connected. As the electrical impedance across thecollector-emitter of Q3 increases and as the voltage temporarilyincreases at the collector of Q3 due to the current flow therethrough,diode Q9 will act as a voltage level detector in becomming conductive ata predetermined voltage level. When this occurs, transistor Q7 is alsobiased to its on state via resistor R14. The conduction Q7 further turnsQ3 to its off state and maintains it there during the switchingtransition period. In addition, diode D20 will also conduct as thevoltage rises at the collector of Q3 thus shifting the remaining primarywinding current from the collector emitter circuit of Q3 to thebase-emitter circuit of Q4 to cause Q4 to abruptly saturate and reducethe base elements of switching transistors Q1 and Q2 to a nearly groundpotential through diodes D8 and D7 respectively. As previouslymentioned, Q4 also discharges capacitor C2 through diode D11 andresistor R11. Accordingly, the net result of this combined controlaction is to cause the emitter voltage of Q1 to be abruptly increased atthe same time that the base voltage thereof is abruptly decreased thusabruptly reverse biasing the base-emitter junction of Q1 to effect arapid turn off of this switching transistor.

The stored energy in the magnetic fields of the transformer willsubsequently cause a voltage reversal on all of the transformerwindings. After such a reversal, transistors Q4, Q5 and Q7 will havecome out of saturation due to a lack of forward biasing in the absenceof current through their respective biasing circuits and base currentwill then be supplied to switching transistor Q2 from the tertiarywinding W3 through resistor R1, Q2, Q3, Z1 and D2. At the same time,forward bias for the base of Q3 is also provided by the tertiary windingW3 through diode D3, resistor R3, Q3, Z1 and D2. In this case, Q2 and Q3have now been turned on so that primary winding current passes throughthe center tap, winding W1, Q2, Q3 and Z1. When the total primarywinding current through Z1 increases sufficiently to trigger Q5, anothertransition switching period will begin and proceed as described above totransition Q2 to its off state and Q1 to its on state by causing theemitter potential of Q2 to rise and simultaneously causing the basepotential of Q2 to fall thus abruptly reverse biasing the base-emitterjunction of Q2.

Diodes D5 and D6 are provided to limit the reverse peak base-emittervoltage across Q1 and Q2 during periods of negative collector current onQ1 and Q2 which occur during switching transition periods because of thetransformer reaction to the current switching transition. An alternatepossibility would involve placing the cathodes of diodes D5, D6 to thecollectors of Q1, Q2 respectively instead of the bases of Q1, Q2.

The secondary winding W4 of the output transformer would be connected toa load such as, for example, a rectifier, etc. As indicated in FIG. 1,the primary, secondary and tertiary windings are magnetically coupledone to another.

The alternate embodiment shown in FIG. 2 is quite similar, in general,to the preferred embodiment of FIG. 1, Accordingly, the same referencenumerals have been utilized in FIGS. 1 and 2 to denote elements havingsimilar functions. The starting circuitry and the basic switching andoperation of the inverter shown in FIG. 2 is quite similar to thatalready described with respect to FIG. 1. The basic difference betweenFIG. 1 and FIG. 2 involves the current detection technique utilized inFIG. 2. Once the inverter of FIG. 2 has been initiated in operation, theprimary winding current flows through, for instance, Q1, Z1 and Q3. Avoltage is then developed across Z1 and Q3 which is proportional to theprimary winding current. A voltage divider Z2 and R7 is connected inparallel across this voltage so as to reflect a desired proportionthereof to the base of transistor Q5 through Z2. Although the idealcharacteristics of Z1 and Z2 are a current sink and voltage clamprespectively, either can be approximated by resistors, diodes,transistors, or combinations thereof, etc., in monolithic integratedstructures as will be appreciated. When the primary winding currentthrough Z1 and Q3 and hence the voltage thereacross reaches a desireddesign limit, Q5 will be turned on as in the embodiment of FIG. 1 toinitiate a sequence of events causing transition between the switchingtransistors Q1 and Q2. In this embodiment, Q5 is already inherentlycontrolled by the increase in impedance of Q3's collector-emittercircuit (and hence as increased voltage across the voltage dividercontrolling Q5) thus Q7 from FIG. 1 has been eliminated in FIG. 2.Otherwise, the switching transition control is the same as previouslydescribed with respect to FIG. 1.

The alternate embodiment shown in FIG. 3 is also quite similar inprinciple to the preferred embodiment of FIG. 1. However, the circuitryin FIG. 3 provides independent base and emitter controls for theswitching transistors Q1 and Q2, each of these independent sets ofcontrols being commonly triggered by a common current detector. Asbefore, elements shown in FIG. 3 having correspondingly counterparts inthe circuitry of FIG. 1 are identified with the same referencecharacters.

The starting circuitry of FIG. 3 is the same as that described inFIG. 1. The starting current phase from Q6 through R8 provides basecurrent to turn on Q3 and, at the same time, through R9 and D10, basecurrent is provided to turn on Q1. Thus, as before, primary windingcurrent is caused to flow through W2, Q1, Q3 and Z1. When the currentthrough Z1 reaches a predetermined level, Q5 will be turned on and, inturn, Q14 will also be turned on through D19 and R22. The correspondingcontrol transistor Q15 for Q2 does not now transition to its on statebecause of the voltage drop across diode D1 which holds the emitter ofQ15 below ground potential.

As Q14 is thus turned on, Q11 is also provided with base current andthus turned on through resistor R23 which, in turn, turns Q3 off causingthe electrical impedance between the collector-emitter of Q3 to riseand, accordingly, to cause a corresponding rise in the emitter voltageof Q1. The resulting increased voltage drop across R25 provides enoughbase current to maintain Q11 in its on state during the switchingtransition period. Furthermore, the increased voltage at the emitter ofQ1 also turns on transistors Q13 and Q16, the latter of which abruptlylowers the base voltage of Q1. Accordingly, the result of thiscombination of actions is to abruptly raise the emitter voltage of Q1while simultaneously and synchronously abruptly lowering the basevoltage of Q1 thus reverse biasing the base-emitter junction of Q1 andcausing a quick and efficient transition of its off state. TransistorQ13 is utilized to provide and additional diode voltage drop in serieswith the base of Q16 to insure that Q16 does not prematurely turn onand, in addition, to periodically discharge starting capacitor C2through R11. Since Q12 is inactivated during this half cycle, it doesnot affect operation at this time.

Subsequently, in the switching transition period, the voltage on thetransformer windings will reverse due to the stored magnetic energytherein thus allowing the primary winding current to flow through Q2 dueto the forward biasing of Q2 and Q8 by the current now supplied bytertiary winding W3 in a manner completely analogous to that alreadydiscussed with respect to earlier embodiments of this invention. Sincethe circuit of FIG. 3 is completely symmetric with respect to Q2, thesecond half cycle and all succeeding cycles of inverter operation in thecircuit of FIG. 3 should now be apparent.

Components R18, R19, R16, R17, R5 and R15 are included to guarantee thatQ14, Q15, Q10, Q11, Q16 and Q9 respectively remain off in the absence ofany definite base current thereto.

The alternate inverter circuitry shown in FIG. 4 involves yet anothertype of current detecting arrangement. Here, most of the circuit isidentical with that already discussed in FIG. 1 and the same referencenumerals are utilized for corresponding parts in the two figures.

It will be noted that FIG. 4 does not include the impedance Z1 as thecurrent measuring element. Rather, an inverting current source Q3-Q5 isutilized as the peak current detector. No special impedance element suchas Z1 is required since the Q3-Q5 combination completely provides acurrent sensing means. The direct connection between the collector of Q5and the base of Q3 and of Q5 provides an inverting current source. Byfurther selecting the active area of transistor Q3 to have apredetermined ratio to the active area of transistor Q5 (e.g., to makeQ3 roughly 100 times as large as Q5) a predetermined current invertinggain (e.g., 100) is obtainable. That is, where the ratio is 100 to 1, if1 mA is supplied from R3, Q3 will be a 100 mA current source.

Once started, Q3 will remain in saturation until the collector-emittercurrent therein is equal to the current in R3 times the gain of theQ3-Q5 current inverting source. At this point, transistor Q3 becomesactive thus causing the collector of Q3 to rise in voltage withincreasing current. Once this increasing voltage is detected by diodesD9, D20, etc., Q7 is turned on and Q3 is thereby turned off againdiverting the primary winding current remaining to the base of Q4 withthe ensuing switching action being exactly as is already described withrespect to FIG. 1.

The portion of control circuitry shown in FIG. 5 illustrates theprovision of substantial hysteresis in the control circuitry to achievean especially effective and insured switching control over a switchingtransistor such as Q5' shown in FIG. 5. For instance, it has been notedthat in some instances it is desirable to provide such hysteresis if theinterwinding capacitance of the transformer is large or if the switchingcharacteristics of switching transistor Q5' are extremely fast. In suchcases, it is sometimes possible to completely turn Q4' off even thoughthere may still be sufficient base drive voltage available acrosstertiary winding W3 to partially turn Q5' back on again before thesuccessful completion of the desired switching transition period. Toavoid this potential problem, it is possible to build in hysteresiswithin the control circuitry so that the switching transistor Q5' isforced to remain in its off state so long as there is any remainingvoltage across tertiary winding W3 in a sense that might potentiallyprovide forward bias current therefor.

As the tertiary winding W3 supplies forward bias base current to Q5'through R4', control transistors Q2', Q3' and Q4' are all off. In thisparticular embodiment, the primary winding current flows through Q5' andthe parallel combination of Q1' and R1'. As the current builds in theprimary winding and hence in Q5' and the parallel combination of Q1' andR1', the voltage across the base-emitter junction of Q2' increasessufficiently to turn Q2' on at a predetermined peak current level. Atthis time, control transistor Q1' then turns off causing all of theremaining primary winding current to flow through R1' and Q2'.Accordingly, at this time, the voltage drop across R1' increasessignificantly to insure that Q2' and Q4' are turned on. Of course, inresponse to turning Q4' on, Q3' is also turned on. As may be appreciatedfrom FIG. 5, the net result of these actions is, as before, to cause theemitter voltage of the switching transistor to rise while,simultaneously, significantly lowering the base voltage thereof thusabruptly reverse biasing the base-emitter junction of the switchingtransistor to cause the desired switching transition.

In addition, transistors Q3' and Q4' form a current sensitive latchmeans which operates in a manner similar to an SCR thus remaining onuntil the voltage across tertiary winding W3 actually reverses thuslowering the current through Q3', Q4' below the predetermined levelnecessary to maintain it in its on condition.

Although the circuit of FIG. 5 would work without Q1', its provisionprovides a faster switching transition period.

A more complete inverter circuit employing the SCR type of shutdowntechnique explained in FIG. 5 is shown in the detailed circuitry of FIG.6. The FIG. 6 circuit also provides a common current sensing means.

The starting circuitry is not shown in FIG. 6. Accordingly, theexplanation of FIg. 6 will begin with an assumption that transistors Q1and Q10 have been turned on. As the primary winding current through W2increases to a predetermined level, the other transistors will remainoff. However, as the predetermined current level is attained, transistorQ3 will turn on. With transistor Q3 turned on, the bases of both Q6 andQ9 are lowered. However, Q9 is not turned on since it is still reversebiased at this point due to the voltage across W3. However, Q6 is turnedon in response to the turn on of Q3.

The turning on of Q6 further results in turned on Q5 and Q4 as may beappreciated from FIG. 6. At the same time, Q10 is turned off.Accordingly, as in the earlier discussed embodiment, the emitter voltageof Q1 is forced upwardly while the base voltage of Q1 is abruptlylowered to thus reverse bias the base-emitter junction of Q1 and forcethe desired switching transition. In addition, the PNP and NPNtransistors Q6 and Q5 respectively are connected as shown in FIG. 6 asan SCR type of circuit (explained in more detail with respect to FIG.5). Accordingly, Q5 and Q6 will remain on until the voltage crosstertiary winding W3 actually reverses thus lowering the currenttherethrough below the threshold value necessary to maintain this SCRtype of arrangement in its on condition.

Accordingly, the base-emitter voltage on Q1 is reverse biased as long asthere is any main current through Q1 and this reverse biasing ismaintained so long as there is any base voltage in the positivedirection with respect to Q1 across the tertiary winding W3. Thesymmetrical operation of the remaining component of the FIG. 6 circuitshould now be appreciated without further discussion.

Although only a few specific embodiments of this invention have beendescribed in detail above, those in the art will appreciate that manymodifications and variations of these exemplary embodiments may be madewithout materially departing from the novel and advantageous features ofthis invention. Accordingly, all such variations and modifications areintended to be included within the scope of this invention ad defined bythe appended claims.

What is claimed is:
 1. An electrical inverter circuit for converting ad.c. electrical input into an a.c. electrical output, said invertercircuit comprising:a transformer structure having secondary windingmeans for supplying said electrical output and a primary winding means,said winding means being magnetically coupled to each other throughmagnetic circuit means, active element switch means electricallyconnected to said primary winding means and electrically connectable tosaid d.c. electrical input for alternately switching said d.c.electrical input to said primary winding means for producingcorresponding varying magnetic fields in said magnetic circuit means andthereby producing said a.c. electrical output in said secondary windingmeans, and electrical control means electrically connected to saidactive element switch means for monitoring the magnitude of electricalcurrent flowing in said primary winding means and controlling saidalternate switching operation in response to the detection of current insaid primary winding in excess of a predetermined level, said electricalcontrol means including a further controllable active element means incircuit with said active element switch means such that the primarywinding current also flows therethrough and synchronous control meansfor synchronously controlling said further active element means so as toincrease the electrical impedance thereof during at least a portion ofeach switching transition of said active element switch means.
 2. Anelectrical inverter circuit as in claim 1 wherein:said active elementswitch means comprises two transistor devices each having base, emitterand collector elements where the collector-emitter circuits of each areseparately connected to the primary winding means so as to causediffering current flows therein when respectively controlled to an onstate and where the collector-emitter circuits of each are commonlyconnected in circuit with said further controllable active elementmeans, said electrical control means and said synchronous control meanscomprises a current measuring element connected serially in said commoncollector-emitter circuit with said further controllable active elementmeans and current level detection means electrically connected to saidcurrent measuring element, and said current level detection means isalso electrically connected to said further controllable active elementmeans for substantially simultaneously increasing the electricalimpedance thereof upon the detection of said predetermined level.
 3. Anelectrical inverter circuit as in claim 2 wherein said furthercontrollable active element means comprises a transistor device havingbase, emitter and collector elements where the collector-emitter circuitthereof is connected in said common collector-emitter circuit and wherethe base thereof is connected to said current level detection means. 4.An electrical inverter circuit as in claim 2 wherein said currentmeasuring element comprises a device having a predetermined electricalimpedance.
 5. An electrical inverter circuit as in claim 2 wherein saidcurrent level detection means comprises a transistor device having base,emitter and collector elements where the base element thereof isconnected to said current measuring element and where thecollector-emitter circuit thereof is connected in circuit with the baseelements of said active element switch means.
 6. An electrical invertercircuit as in claim 2 wherein said electrical control means furthercomprises:voltage detection means connected to said further controllableactive element means and in circuit with the base elements of saidactive element switch means for detecting said increase in electricalimpedance by detecting a corresponding temporary voltage rise acrosssaid further controllable active element during current switchingtransistion and for substantially dissipating any forward bias currentsat said base elements in response thereto.
 7. An electrical invertercircuit as in claim 6 further comprising an additional means connectedfor control by said voltage detection means and connected to maintainthe increased impedance of said further controllable active element inresponse to said detected voltage rise.
 8. An electrical invertercircuit as in claim 2 wherein said current level detection means iselectrically connected in parallel across the serial connection of saidcurrent measuring element and said further controllable active element.9. An electrical inverter circuit as in claim 8 wherein said currentlevel detection means comprises a voltage divider and a voltagesensitive device connected for control thereby.
 10. An electricalinverter circuit as in claim 1 wherein:said active element switch meanscomprises two transistor devices each having base, emitter and collectorelements where the collector-emitter circuits of each are separatelyconnected to the primary winding means so as to cause differing currentflows therein when respectively controlled to an on state, said furthercontrollable active element means comprises two separate elementsrespectively in series circuit with said collector-emitter circuits,said electrical control means and said synchronous control meanscomprises a current measuring element connected in common with saidseparate elements and current level detection means electricallyconnected in circuit with said current measuring element, and saidcurrent level detection means is also electrically connected to controlboth of said separate elements for substantially simultaneouslyincreasing the electrical impedances thereof upon detection of saidpredetermined level.
 11. An electrical inverter circuit as in claim 10wherein said electrical control means further comprises separate basebias control means each separately in circuit with its respectivelyassociated active switch means base element and connected for control bysaid current level detection means for substantially dissipating anyforward bias currents at the respectively associated base elements inresponse to the detection of said predetermined level.
 12. An electricalinverter circuit as in claim 1 wherein said electrical control meanscomprises:current monitoring means connected to a control lead of saidfurther controllable active element for automatically detecting thecurrent level flowing therethrough and for automatically controlling theelectrical impedance thereof when a predetermined current level isdetected.
 13. An electrical inverter circuit as in claim 12 wherein saidcurrent monitoring means comprises an inverting current source.
 14. Anelectrical inverter circuit as in claim 13 wherein:said furthercontrollable active element comprises a transistor device having base,emitter and collector elements where the collector-emitter circuitthereof is connected to carry said primary winding current, said currentmonitoring means comprises another transistor device having base,emitter and collector elements where said base elements are electricallyconnected together, where at least one pair of said emitter andcollector elements are electrically connected together and where theremaining element of said another transistor device is electricallyconnected to said common base connection and where said transistordevices have respectively associated active areas having a predeterminedarea ratio.
 15. An electrical inverter circuit as in claim 12 whereinsaid electrical control means comprises:voltage detection meansconnected to said further controllable active element means and incircuit with the control elements of said active element switch meansfor detecting said increase in electrical impedance by detecting acorresponding temporary voltage rise across said further controllableactive element during current switching transistion and forsubstantially dissipating any forward bias currents at said controlelements in response thereto.
 16. An electrical inverter circuit as inclaim 1 wherein said electrical control means includes hysteresis meansconnected to insure that the active element switch means are positivelycontrolled to their off state during switching transition periods. 17.An electrical inverter circuit as in claim 16 wherein said hysteresismeans comprises a current senstive latch connected to the controlelements of said active element switch means for dissipating currenttherefrom once triggered to a conductive state by detection of saidpredetermined level until the level of such current falls below apredetermined lower limit whereupon said current sensitive latchautomatically reverts to a non-conductive state.
 18. An electricalinverter circuit as in claim 17 wherein said current sensitive latchcomprises an NPN and PNP transistor device having respectivelyinterconnected base and collector elements.
 19. An electrical invertercircuit as in claim 16 wherein:said active element switch means comprisetwo transistor devices having base, emitter and collector elements, andsaid hysteresis means comprise separate current sensitive latch meansrespectively connected in circuit with the base elements of said activeelement switch means for dissipating current therefrom once triggered toa conductive state by detection of said predetermined level until thelevel of such current falls below a predetermined lower limit whereuponsaid current sensitive latch means each automatically revert to anon-conductive state.
 20. An electrical inverter circuit as in claim 19wherein said current sensitive latch means each comprise an NPN and PNPtransistor device having respectively interconnected base and collectorelements..Iadd.
 21. An electrical switching circuit for efficientlyinterrupting current flow between a first terminal and a second terminalcomprising, in combination:a first transistor switching elementincluding a collector, a base, and an emitter, the collector of saidfirst element being connected to said first terminal; a second switchingelement connected, in series, between said emitter and said secondterminal; and control circuit means which function to initiateinterruption of current flow between said first terminal and said secondterminal by removing a control current from said base and simultaneouslyincreasing the electrical impedance of said second switching element..Iaddend..Iadd.
 22. The circuit of claim 21 wherein said secondswitching element includes a second transistor. .Iaddend. .Iadd.
 23. Thecircuit of claim 22 wherein said control circuit means include a thirdswitching element, connected between said base and said second terminal..Iaddend..Iadd.
 24. The circuit of claim 23 wherein said third switchingelement is a transistor and wherein said control circuit means functionto force said second transistor into a non-conducting state and tosimultaneously force said third transistor into a conducting state..Iaddend..Iadd.
 25. The circuit of claim 24 wherein said first switchingelement, said second switching element, and said third switching elementare npn transistors and wherein said first terminal is positive withrespect to said second terminal. .Iaddend..Iadd.
 26. A method forshutting off electric current flow from a first terminal through aseries semiconductor switch to a second terminal comprising the stepsof: removing current from a control element of said semiconductorswitch; and simultaneously increasing the impedance of a first auxiliaryswitching element connected in series between a emitter of saidsemiconductor switch and said second terminal. .Iaddend. .Iadd.
 27. Themethod of claim 26 wherein said first auxiliary switching element is afirst transistor and said step of increasing the impedance of said firstswitching element includes the step of biasing said first transistorinto a nonconducting state. .Iaddend..Iadd.
 28. The method of claim 26wherein said step of removing current includes decreasing the impedanceof a second auxiliary switching element connected between said controlelement and said second terminal. .Iaddend..Iadd.
 29. The method ofclaim 28 wherein said first auxiliary switching element is a firsttransistor and said second auxiliary switching element is a secondtransistor. .Iaddend..Iadd.
 30. The method of claim 28 wherein saidfirst auxiliary switching element is a transistor and said secondauxiliary switching element is a silicon controlled rectifier. .Iaddend.